Field
The following relates to integrated circuits, and more particularly to integrated circuits that have multiple clock domains.
Related Art
Synchronous digital circuits use clock signals to synchronize pieces of circuitry that propagate data. For example, a stage in a pipelined processor may include some combinatorial logic that uses inputs from a set of latches, which are clocked by a clock for the clock domain in which the combinatorial logic exists, and outputs data which is latched by another set of latches that feeds a subsequent pipeline stage. A complex integrated circuit may contain multiple clock domains, each with circuitry synchronized to a clock in that clock domain. Multiple clock domains present an opportunity to more granularly adjust operating frequency of different portions of a complex integrated circuit, by independently varying clock frequencies in different clock domains. A principal reason for adjusting clock operating frequency is to opportunistically reduce power consumption. However, considerations relating to maintaining correctness of operation and other optimizations arise when implementing such dynamic clock frequency adjustments.